FPGA Tron Game
Nov 2025 · Solo · Coursework
A real-time two-player Tron lightcycle game running on a DE10-Lite FPGA. Game logic and collision detection run in C on the Nios V (RISC-V) soft core; the display is driven over a memory-mapped VGA interface.
The renderer uses a custom double-buffered pipeline: frames compose off-screen and swap on the screen refresh, which keeps 60 Hz output clean. Inputs are interrupt-driven so button presses register cleanly even while the main loop is busy with collision checks.
Specs
- Platform
- DE10-Lite FPGA
- Processor
- Nios V soft core (RISC-V)
- Language
- C
- Display
- VGA via memory-mapped control registers, 60 Hz
- Renderer
- Custom double-buffered pipeline (no screen tearing)
- Input
- Hardware-interrupt-driven for precise timing
Implementation
The game runs as a tight loop on the Nios V soft core: each tick advances both lightcycles, checks the trail map for collisions, and writes the new frame to the back buffer. Bit masking on the VGA memory-mapped control registers handles pixel writes and the buffer swap directly, without going through a separate framebuffer driver.
Inputs are routed through hardware interrupts rather than polled, so a button press registers on the next tick regardless of where the main loop is sitting. With the double-buffer swap synced to the screen refresh, frames stay clean at 60 Hz.